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  • JOURNAL ARTICLE
    Liu Y, Pereira JL, Constandinou TG, 2018,

    Event-driven processing for hardware-efficient neural spike sorting

    , JOURNAL OF NEURAL ENGINEERING, Vol: 15, ISSN: 1741-2560
  • JOURNAL ARTICLE
    Luan S, Williams I, Maslik M, Liu Y, De Carvalho F, Jackson A, Quiroga RQ, Constandinou TGet al., 2018,

    Compact standalone platform for neural recording with real-time spike sorting and data logging.

    , J Neural Eng, Vol: 15

    OBJECTIVE: Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. APPROACH: We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. MAIN RESULTS: The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. SIGNIFICANCE: The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable outp

  • JOURNAL ARTICLE
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2018,

    Continuous-time acquisition of biosignals using a charge-based ADC topology

    , IEEE Transactions on Biomedical Circuits and Systems, Pages: 1-12, ISSN: 1932-4545

    This paper investigates Continuous-Time (CT) signal acquisition as an activity-dependent and non-uniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by non-uniform quantisation to commonly recorded biological signal fragmentsallowing a compression ratio of 5 and 26 when applied to Electrocardiogram (ECG) and Extracellular Action Potential (EAP) signals respectively. We describe several desirable properties of CT sampling including bandwidth reduction, elimination/reduction of quantisation error and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT Analogue-to-Digital Converter (CT ADC) that has been optimised for the acquisition of neural signals. This has been implemented in a commercially-available 0.35µm CMOS technology occupying a compact footprint of 0.12mm². Silicon verified measurements demonstrate an 8-bit resolution and a 4kHz bandwidth with static power consumption of 3.75µWfrom a 1.5V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39pJ energy per conversion.

  • BOOK CHAPTER
    Williams I, Leene L, Constandinou TG, 2018,

    Next Generation Neural Interface Electronics

    , Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
  • CONFERENCE PAPER
    Davila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017,

    Real-time Clustering Algorithm that Adapts to Dynamic Changes in Neural Recordings

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693, ISSN: 0271-4302
  • CONFERENCE PAPER
    De Marcellis A, Palange E, Faccio M, Stanchieri GDP, Constandinou TGet al., 2017,

    A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants

    , Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
  • CONFERENCE PAPER
    Feng P, Constandinou TG, Yeon P, Ghovanloo Met al., 2017,

    Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
  • CONFERENCE PAPER
    Gao C, Ghoreishizadeh S, Liu Y, Constandinou Tet al., 2017,

    On-chip ID Generation for Multi-node Implantable Devices using SA-PUF

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681, ISSN: 0271-4302
  • CONFERENCE PAPER
    Ghoreishizadeh SS, Haci D, Liu Y, Constandinou TGet al., 2017,

    A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication

    , 8th IEEE Latin American Symposium on Circuits & Systems (LASCAS), Publisher: IEEE
  • JOURNAL ARTICLE
    Ghoreishizadeh SS, Haci D, Liu Y, Donaldson N, Constandinou TGet al., 2017,

    Four-Wire Interface ASIC for a Multi-Implant Link

    , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328
  • CONFERENCE PAPER
    Guven O, Eftekhar A, Kindt W, Constandinou TGet al., 2017,

    Low-Power Real-Time ECG Baseline Wander Removal: Hardware Implementation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302
  • CONFERENCE PAPER
    Haci D, Liu Y, Constandinou TG, 2017,

    32-Channel Ultra-Low-Noise Arbitrary Signal Generation Platform for Biopotential Emulation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701, ISSN: 0271-4302
  • CONFERENCE PAPER
    Leene L, Constandinou TG, 2017,

    A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 2379-447X

    This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterizationand interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.

  • JOURNAL ARTICLE
    Leene LB, Constandinou TG, 2017,

    A 0.016 mm(2) 12b Delta Sigma SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

    , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 64, Pages: 2655-2665, ISSN: 1549-8328
  • JOURNAL ARTICLE
    Leene LB, Constandinou TG, 2017,

    Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

    , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 64, Pages: 3003-3012, ISSN: 1549-8328
  • JOURNAL ARTICLE
    Liu Y, Luan S, Williams I, Rapeaux A, Constandinou TGet al., 2017,

    A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545

    Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.

  • CONFERENCE PAPER
    Luo J, Firfilionis D, Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2017,

    Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169
  • CONFERENCE PAPER
    Maslik M, Liu Y, Lande TSB, Constandinou TGet al., 2017,

    A Charge-Based Ultra-Low Power Continuous-Time ADC for Data Driven Neural Spike Processing

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302
  • CONFERENCE PAPER
    Mifsud A, Haci D, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    Adaptive Power Regulation and Data Delivery for Multi-Module Implants

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587
  • CONFERENCE PAPER
    Szostak K, Mazza F, Maslik M, Feng P, Leene L, Constandinou TGet al., 2017,

    Microwire-CMOS Integration of mm-Scale Neural Probes for Chronic Local Field Potential Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 492-495

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